Fabrication Process For Increased Capacitance In An Embedded DRAM Memory

ABSTRACT

An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.

RELATED APPLICATIONS

The present application is a divisional of U.S. patent application Ser.No. 11/050,988 filed Feb. 3, 2005, entitled “Fabrication Process ForIncreased Capacitance In An Embedded DRAM Memory” by Dennis Sinitsky andFu-Chieh Hsu. This application is related to commonly-owned U.S. Pat.No. 6,642,098 issued on Jun. 6, 2003, and commonly-owned U.S. Pat. No.6,573,548 issued in Nov. 4, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to dynamic random access memory (DRAM).Moreover, the present invention relates to DRAM fabricated by slightlymodifying a conventional one-transistor static random access memory(1T-SRAM-Q) process, which in turn is a slight modification of aconventional logic process.

2. Related Art

FIG. 1 shows a schematic of a conventional DRAM cell 1 that isfabricated using a conventional logic process. As used herein, aconventional logic process is defined as a semiconductor fabricationprocess that uses only one layer of polysilicon and provides for eithera single-well or twin-well structure. DRAM cell 1 consists of p-channelMOS access transistor 2 (referred to here as pass gate), p-channel MOStransistor 3, word line electrode 4 (which is coupled to the gateterminal of access transistor 2), and bit line electrode 5 (which iscoupled to the drain terminal of access transistor 2). P-channeltransistor 3 is configured to operate as a charge-storage capacitor,with the source and drain of this transistor 3 being commonly connected.P-channel transistor 3 is hereinafter referred to as a cell capacitor.

FIGS. 2A-2D are cross sectional views illustrating an embedded DRAMprocess flow resulting in the manufacture of an array of DRAM cells(identical to DRAM cell 1) in memory array region 10 and conventionallogic devices in logic region 11. As shown in FIGS. 2A-2D, the array ofDRAM cells are fabricated side-by-side on the same chip withconventional logic devices.

As shown in FIG. 2A, a mask layer 1200 is formed over p-type substrate1000. A photoresist mask 1300 is formed over mask layer 1200 asillustrated. The openings in photoresist mask 1300 define the locationsof subsequently formed shallow trench isolation (STI) structures.

As shown in FIG. 2B, an etch is performed through photoresist mask 1300,thereby removing the exposed portions of mask layer 1200. Photoresistmask 1300 is stripped, and a shallow trench etch is then performed to adepth D_(STI) through the patterned mask layer 1200.

As shown in FIG. 2C, patterned mask layer 1200 is removed, n-type wellregion 1100 is formed, the trenches formed in FIG. 2B are filled with aSTI dielectric 120, such as SiO₂. STI dielectric 120, which has a depthD_(STI), is used to isolate active circuitry, including logic gates andmemory cells. Another patterned mask layer 1320 is formed over theresulting structure. Patterned mask layer 1320 includes an opening,which exposes a portion of n-well region 1100 and STI dielectric 120 asillustrated. An etch is performed through this opening, thereby removinga portion of the exposed STI dielectric 120, and exposing a sidewallsection of the trench. As described below, this etch allows theformation of a folded capacitor structure. This folded capacitorstructure saves cell area while still maintaining large capacitance,thereby allowing the resulting DRAM memory cell to operate properly. STIdielectric 120 maintains a thickness T₁ at the bottom of the trench. Theremaining thickness T₁ of the recessed STI region is thick enough toprevent formation of an inversion layer directly under the recessedregion, thereby isolating memory cells adjacent to the recessed STIdielectric 120.

A P− type implant is performed through the opening of patterned masklayer 1320, thereby forming P− doped layer 140 in well region 1100. Notethat N-well 1100 isolates the array memory cells from other circuits onthe die and from the large body of substrate 1000, therefore improvingnoise immunity and soft-error-rate of the memory.

As shown in FIG. 2D, patterned mask layer 1320 is removed, andprocessing continues with the formation of gate dielectric layers130-131, conductive elements 101, 100A, 100B and 100C (with adjacentsidewall spacers), P− regions 150, 160 and 161, P+ regions 170-171,metal salicide regions 180-181, and salicide blocking layer 190. In oneembodiment, conductive elements 101, 100A, 100B and 100C are formed overgate dielectric 130-131 using the conventional logic process polysiliconlayer. Salicide regions 180-181 are simultaneously formed in both memoryand logic areas, thereby forming high-performance transistors. It isdesirable to exclude salicide from the charge storage regions 150 and140; therefore, salicide blocking layer 190 is used to prevent salicideformation in these regions. Logic devices formed in area 11 also containconventional logic LDD and source/drain diffusions 161 and 171,respectively.

Conductive element 100A forms a gate electrode of a p-channel transistorcorresponding with access transistor 2 (FIG. 1). Gate dielectric 130,salicide layer 180, P+ diffusion region 170 and P− diffusion regions 150and 160 form the remaining elements of this access transistor. Salicidelayer 180 and P+ diffusion region 170 provide reduced contact resistancefor an associated bit line (not shown). P− type layer 140 and conductiveelement 100B are separated by gate dielectric 130, thereby forming acapacitor corresponding with cell capacitor 3 (FIG. 1). P− diffusionregion 150 couples the access transistor to MOS capacitor 3. The cellcapacitor stores charge in an inversion layer in the substrate locatedunder conductive element 100B. This inversion layer is formed byapplying a large negative voltage to capacitor gate 100B.

Although FIG. 2D only illustrates PMOS logic devices, it is understoodthat NMOS logic devices outside of N-well 1100 are also part of theintegrated circuit.

The fabrication process of FIGS. 2A-2D is described in more detail inconnection with FIGS. 3G-3S of U.S. Pat. Nos. 6,642,098 and 6,573,548.Hereafter, this fabrication process is referred to as the “1T-SRAM-Qprocess”.

The conventional 1T-SRAM-Q memory process shown in FIGS. 2A-2D has onemajor shortcoming. Namely, as the technology scales in sub-90 nmdimensions, the STI thickness (D_(STI)) gradually decreases. At the sametime, the thickness T₁ cannot arbitrarily decrease because thisthickness is required to prevent cross-cell leakage within the processvariation of memory cell parameters. It is therefore challenging tomaintain acceptable cell capacitance, which enables proper DRAM memoryread operations, as technology scales.

It would therefore be desirable to have an embedded DRAM process, whichresolves the above-described capacitance scaling limitation.

SUMMARY

Accordingly, the present invention provides an improved method offorming an embedded DRAM system including DRAM cells and logictransistors on the same semiconductor substrate, wherein each of theDRAM cells includes an access transistor and a capacitor structure. Themethod includes forming a plurality of shallow trenches having a firstdepth in a logic area of the substrate, and forming a plurality of deeptrenches having a second depth, greater than the first depth, in amemory array area of the substrate. Dielectric material is deposited inthe shallow trenches, thereby forming shallow trench isolation regions,which isolate logic transistors in the logic region. Similarly,dielectric material is deposited in the deep trenches, thereby formingdeep trench isolation regions, which isolate DRAM cells in the memoryarray region.

Cavities are etched in the deep trench isolation regions, therebyexposing sidewall regions of the substrate. A dopant can optionally beimplanted into the exposed sidewall regions, thereby creating inversionregions in the exposed sidewall regions. A dielectric layer, which formsthe capacitor dielectric of the DRAM cell capacitors, is formed over theexposed sidewall regions. A conductive layer, such as polysilicon, isdeposited over the dielectric layer, filling the cavities etched in thedeep trench isolation regions. This conductive layer is patterned,thereby forming electrodes of the cell capacitors, gate electrodes ofthe access transistors, and gate electrodes of the logic transistors.The deep trench isolation regions enable a large capacitor area in arelatively small layout area, while maintaining the required isolationthickness T1 at the bottom of the deep trench.

The shallow trenches and the deep trenches can be formed in variousmanners in different embodiments of the present invention. For example,an intermediate depth etch, having a depth equal to the second depthminus the first depth, can be performed in locations where the deeptrenches are to be formed. Subsequently, a shallow depth etch, having adepth equal to the first depth, can be performed in locations where boththe shallow and deep trenches are to be formed.

In another example, a shallow depth etch, having a depth equal to thefirst depth, can be performed in locations where both the shallow anddeep trenches are to be formed. Subsequently, an intermediate depthetch, having a depth equal to the second depth minus the first depth,can be performed in locations where the deep trenches are to be formed.

In yet another example, a shallow depth etch, having a depth equal tothe first depth, can be performed in locations where the shallowtrenches are to be formed. A deep etch, having a depth equal to thesecond depth, can be performed in locations where the deep trenches areto be formed.

The present invention will be more fully understood in view of thefollowing description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic of a conventional DRAM cell that is fabricatedusing a conventional logic process.

FIGS. 2A-2D are cross sectional views illustrating an embedded DRAMprocess flow resulting in the manufacture of an array of DRAM cells in amemory array region, and conventional logic devices in a logic region.

FIGS. 3A-3P are cross sectional views of a DRAM cell and a conventionallogic transistor during various states of fabrication in accordance withone embodiment of the present invention.

FIG. 3Q is a top view of an array of DRAM cells, formed using theprocess flow of FIGS. 3A-3P, in accordance with one embodiment of thepresent invention.

FIGS. 4A and 4B are cross sectional views illustrating an alternatemethod for forming shallow and deep isolation trenches in accordancewith the present invention.

FIGS. 5A and 5B are cross sectional views illustrating an alternatemethod for forming the desired shallow and deep trenches of the presentinvention.

DETAILED DESCRIPTION

The present invention provides a memory system that includes DRAM cellsconsistent with the circuit schematic of FIG. 1, along with conventionallogic transistors fabricated on the same chip. These DRAM cells andlogic transistors are fabricated by slightly modifying a conventionallogic process or the 1T-SRAM-Q process.

FIGS. 3A-3P are cross sectional views of a DRAM cell and a conventionallogic transistor during various states of fabrication in accordance withone embodiment of the present invention.

FIG. 3A shows a p-type semiconductor substrate 300, which is separatedinto DRAM cell array region 30 and logic device region 31. Logic deviceregion 31 is designated as all area in the non-memory part of theintegrated circuit, as well as the area of the DRAM memory circuitrythat does not include the DRAM cell array. In the described example,substrate 300 has a <1,0,0> crystalline orientation and a dopantconcentration of about 1×10¹⁶/cm³. Other crystal orientations andconcentrations can be used in other embodiments of the invention. Inaddition, the conductivity types of the various regions can be reversedin other embodiments with similar results.

A hard mask layer 320, for example silicon nitride is formed oversubstrate 300. A photoresist layer 321 is then deposited over hard maskfilm 320. This photoresist layer 321 is exposed and developed, therebycreating openings 322-323. These openings 322-323 define the locationsof subsequently formed memory area isolation regions. An etch isperformed through openings 322-323, thereby forming correspondingopenings 324-325 through the exposed portions of hard mask layer 320(FIG. 3B). Photoresist layer 321 is then stripped.

As shown in FIG. 3B, after photoresist layer 321 has been stripped, aninitial trench etch is performed through the openings 324-325 in hardmask layer 320. This etch forms initial trenches 331-332, each having anintermediate depth equal to D_(INT). As described below, theseintermediate depth trenches 331-332 are subsequently made deeper andfilled with a dielectric material to implement memory area siliconisolation.

As shown in FIG. 3C, a photoresist layer 335 is formed over theresulting structure. Photoresist layer 335 is exposed and developed toform opening 336. Opening 336, which is aligned with an edge ofintermediate depth trench 332, exposes a portion of the underlying hardmask layer 320. An etch is performed through opening 2311, therebyforming an opening 337 through the exposed portion of hard mask layer320.

Photoresist layer 335 is then stripped, and a conventional shallowtrench isolation (STI) etch is performed through hard mask layer 320 toa depth of D_(STI). At this time, intermediate depth trenches 331-332are made deeper by an amount approximately equal to D_(STI), therebyforming deep trenches 341-342. These deep trenches 341-342 have a depthD_(DTI), which is approximately equal to D_(INT)+D_(STI). Shallow trench343, having a depth of D_(STI), is formed in the location previouslydefined by opening 336 of photoresist mask 335. In the describedembodiment, the crystalline structure of substrate 300 causes thesidewalls of trenches 341-343 to exhibit angles of about 80 degrees.

In another embodiment of a present invention, completely separatelithography and etch steps can be used to define shallow trench 343 anddeep trenches 341-342.

As shown in FIG. 3E, a dielectric layer 345, such as silicon oxide, isthen deposited over the resulting structure, thereby filling trenches341-343 and covering hard mask layer 320. Achemical-mechanical-polishing (CMP) planarization step is then performedto planarize dielectric layer 345, with hard mask layer 320 acting as astopper layer, in a manner consistent with manufacturing ofshallow-trench-isolation (STI) in a conventional logic process. As shownin FIG. 3F, at the end of the CMP planarization step, the upper surfacesof the dielectric layer 345 are substantially co-planar with the uppersurface of substrate 300. The portion of dielectric layer 345 remainingin deep trench 341 is labeled as dielectric region 351. The portion ofdielectric layer 345 remaining in deep and shallow trenches 342 and 343is labeled as dielectric region 352.

Sacrificial oxidations and well and threshold voltage adjust implantsare then performed in a manner consistent with the conventional logicprocess, notably forming N-well 301 of the DRAM array. In oneembodiment, N-well 301 is formed by a conventional process step such asion implantation, and has a dopant concentration of about 1×10¹⁷/cm³.Although no logic regions outside of N-well 301 are shown in FIG. 3F,the existence of such regions is evident to one of ordinary skill in theart. In another embodiment of the present invention, the DRAM cell arraycan be fabricated in a P-type triple-well and employ NMOS transistors.In this case, a deep N-type well and a triple P-type well are fabricatedin place of N-well 301.

Turning now to FIG. 3G, buffer oxide layer 355 is either retained fromthe STI processing step or thermally grown over the upper surface of theresulting structure. In the described embodiment, oxide layer 355 issilicon oxide having a thickness in the range of about 5 to 20 nm.However, this thickness can vary depending on the process being used.

Photoresist mask 356, having opening 357, is formed over buffer oxidelayer 355 using well known processing techniques. Opening 357 is locatedpartially over n-well 301 and partially over field dielectric region351.

As illustrated in FIG. 3G, an etch is performed through the opening 357of photoresist mask 356, thereby removing the exposed portion of oxidelayer 355. The etch also removes an exposed portion of dielectric region351, thereby creating a cavity 360 in dielectric region 351. At the endof the etch, dielectric region 351 has a thickness T1 under cavity 360in the range of about 50 to 200 nm. This thickness T1 is selected to bethick enough to isolate adjacent DRAM cells in memory array region 30.The etchant is highly selective to silicon, such that n-type well 301 isnot substantially removed during the etch. In one embodiment, this etchis a timed etch.

As illustrated by FIG. 3G, an optional p− type ion implant is performedthrough opening 357 of photoresist mask 356. In one embodiment, boron isimplanted at a dosage of 2×10¹³/cm² and an energy of 10-15 KeV. The p−type implant results in the formation of P− capacitor inversion region340. Capacitor region 340 makes the threshold voltage under thesubsequently formed capacitor structure more positive, such that thecapacitor structure can be turned on more easily. That is, P− inversionlayer 340 helps to invert the substrate adjacent to the cell capacitorelectrode and boost performance of the resulting DRAM cell. In theembodiment where a triple-P-well structure is used in place of N-well301, the P− implant is replaced with an N− implant, thereby resulting inan N− inversion layer. In another embodiment, an inversion layer isformed by applying appropriate bias to the gate of the MOS cellcapacitor.

As illustrated in FIG. 3H, photoresist mask 356 and buffer oxide layer355 are stripped, and gate dielectric layers 361 and 362 are then formedover the upper surface of the resulting structure. In the describedembodiment, gate dielectric layers 361 and 362 are thermally grownsilicon oxide having a thickness in the range of about 1.5 to 5 nm.However, this thickness can vary depending on the process being used. Inthe described embodiment, the same gate dielectric layer 361 is used forboth the gate oxide of the access transistor and the dielectric layer ofthe cell capacitor. However, in other embodiments, different layers canbe used to form the gate dielectric layer and the capacitor dielectriclayer. For example, the capacitor dielectric layer can be fabricated tobe thicker than the gate dielectric layer. In another example, thecapacitor dielectric layer can be formed from silicon nitride or acombination of silicon oxide and silicon nitride, while the dielectriclayer is formed only from silicon oxide. The gate dielectric layers 361and 362 can either be identical, or different in thickness and/orcomposition.

From this point forward, the conventional logic process is resumed. Asshown in FIG. 3I, a layer of polycrystalline silicon 363 having athickness in the range of about 100 to 300 nm is deposited over theresulting structure. Polysilicon layer 363 substantially fills cavity360. Photoresist mask 364 is formed over polysilicon layer 363. As willbecome apparent in view of the following description, photoresist mask364 defines the gate electrode of the access transistor, an electrode ofthe cell capacitor, a gate electrode of a logic transistor, and aconductive element in the memory array region 30.

As illustrated in FIG. 3J, polysilicon layer 363 is etched throughphotoresist mask 364, thereby forming logic gate electrode 371, memoryaccess gate electrode 372, capacitor electrode 373 and memory arrayconductor 374. A portion of capacitor electrode 373 remains in cavity360. By forming portions of capacitor electrode 360 on the sidewall ofcavity 360, the area of incidence between capacitor electrode 373 andcapacitor region 340 (i.e., the area of the capacitor) is maderelatively large, while the required layout area of capacitor electrode373 is made relatively small.

As illustrated in FIG. 3K, photoresist mask 364 is stripped, and a p−type ion implant is performed onto the resulting structure. As a result,lightly doped p− type source/drain regions 302-304 are formed in n-well301. P-type source/drain region 304 is continuous with capacitor region340. In addition, polysilicon regions 371-374 receive p-type impuritiesduring this implant.

As illustrated in FIG. 3L, sidewall spacers 305 are formed on theresulting structure. Sidewall spacers 305 are formed using aconventional fabrication process. For example, sidewall spacers 305 canbe formed by depositing a silicon nitride layer over the resultingstructure, an then performing an anisotropic etch on the silicon nitridelayer using conventional processing techniques. After the anisotropicetch is complete, silicon nitride spacers 305 remain.

After silicon nitride sidewall spacers 305 have been formed, a P+photoresist mask (not shown) is formed to define the locations of thedesired P+ regions on the chip. A P+ type ion implant is then performed,thereby forming P+ source/drain regions 312 and 313 (as well as theother desired P+ regions on the substrate). The P+ type ion implantfurther dopes polysilicon regions 371-373. Sidewall spacers 305 preventthe P+ impurity from being implanted in lightly doped source/drainregion 304. Optionally, the P+ photoresist mask (not shown) can includea portion that prevents the P+ impurity from being implanted intolightly doped source/drain region 304. An annealing thermal cycle issubsequently performed to activate the implanted impurities in regions302-304, 312-313 and 340.

Turning now to FIG. 3M, a salicide-blocking dielectric layer 307 (e.g.,silicon oxide) is deposited over the resulting structure. Asalicide-blocking photoresist mask 308 is formed over dielectric layer307. Mask 308 is patterned to expose gate electrode 371, p+ typesource/drain regions 312-313, a portion of gate electrode 372, and aportion of conductive element 374.

As shown in FIG. 3N, dielectric layer 307 is etched, thereby removingthe portions of dielectric layer 307 exposed by mask 308. Morespecifically, polysilicon gate electrode 317, p+ source/drain regions312-313, the left portion of polysilicon gate electrode layer 372, andthe right portion of polysilicon region 374 are exposed.

As illustrated in FIG. 3O, mask 308 is stripped and a refractory metallayer 309, such as titanium or cobalt, is deposited over the resultingstructure. In the described embodiment, titanium is deposited to athickness of about 30 nm. An anneal is subsequently performed, therebycausing the refractory metal layer 309 to react with underlying siliconregions to form metal silicide regions. In FIG. 3O, the only siliconregions underlying refractory metal layer 309 are gate electrode 371,the p+ source/drain regions 312-313, the left portion of polysilicongate electrode 372, and the right portion of polysilicon conductiveelement 374.

The unreacted portions of refractory metal layer 309 are then removed,as illustrated in FIG. 3P. Metal silicide regions 309A, 309B, 309C, 309Dand 309E are formed over gate electrode 371, p+ source/drain regions 312and 313, the left portion of polysilicon gate electrode 372 and theright portion of polysilicon conductive element 374, respectively. It ispreferable to block silicide formation from areas where leakage currentshould be minimized, namely, source/drain region 304 and optionally,polysilicon capacitor electrode 373. Note that dielectric layer 307prevents silicide from being formed in these locations.

Finally, the standard logic backend process well known to one skilled inthe art, consisting of contact, metal, and via formations, is performedand completes the process of fabrication of embedded DRAM integratedcircuit.

The resulting DRAM cell is illustrated in FIG. 3P. The access transistorof this DRAM cell is located in region 381, and the cell capacitorstructure of this DRAM cell is located in region 382. The capacitorstructure has a relatively large surface area because the capacitorstructure is formed in cavity 360 in dielectric region 351. Thisrelatively large surface area results in a relatively large capacitancefor the capacitor structure. However, the capacitor structure consumes arelatively small layout area because the capacitor structure is formedpartially in cavity 360. Advantageously, this DRAM cell can befabricated by making small modifications to a conventional logicprocess. More specifically, the masking step and etch of cavity 360 andthe optional p− ion implant of FIG. 3G are added to a conventional logicprocess to implement a 1T-SRAM-Q process. The masking step and etch usedto create the additional depth of the DTI trenches are added to the1T-SRAM-Q process to implement the process of the present invention.

FIG. 3Q is a top view of an array of DRAM cells, including the DRAM cellof FIG. 3P. Note that the view illustrated by regions 381 and 382 ofFIG. 3P roughly corresponds with the view defined by section line A-A′of FIG. 3Q. Contacts, which provide connections between the drain of anaccess transistor and a bit line, are illustrated as boxes containingX's in FIG. 3Q. Thus, contact 3050 provides a connection fromsource/drain region 313 to a bit line (not shown). Contact 3050 alsoprovides a connection to the drain region of a symmetric DRAM celllocated to the left of the present DRAM cell. In this manner, onecontact provides a connection to two DRAM cells in an array.

Source/drain region 313 and source/drain region 304 are separated bygate electrode 372. The location of mask 356, which defines the boundaryof capacitor region 340, is illustrated in FIG. 3Q. Heavy line 3070,which has a hammerhead shape, defines the sidewall of cavity 360. Cavity360 is located outside of hammerhead-shaped line 3070, but within theboundary defined by mask 356. Thus, the portion of capacitor electrode373 located inside of the hammerhead-shaped line 3070 is located at ahigher elevation than the portion of capacitor electrode 373 locatedoutside of hammerhead-shaped line 3070. The area of capacitor electrode373 is maximized by extending over the sidewall defined by line 3070.Note that capacitor electrode 373 extends to adjacent DRAM cells in FIG.3Q.

FIGS. 4A and 4B are cross sectional views illustrating an alternatemethod for forming the desired shallow and deep trenches of the presentinvention.

As shown in FIG. 4A, a silicon nitride hard mask layer 420 is formedover substrate 300. Hard mask layer 420 generally has the same dimensionas hard mask layer 320, as presented above in connections with FIGS. 3Cand 3D. A shallow trench isolation etch is performed through hard masklayer 420, thereby forming shallow trench regions 441 and 442. Shallowtrench regions 441 and 442 have a depth of D_(STI).

As shown in FIG. 4B, a photoresist mask 444 is formed over the resultingstructure. Photoresist mask 444 covers those regions where shallowtrenches are to be formed, and exposes those regions where deep trenchesare to be formed. An intermediate depth etch is performed throughphotoresist mask 444, thereby extending shallow trench region 441(hereinafter deep trench region 441) and the exposed portion of shallowtrench region 442 (hereinafter deep trench region 443) to a depth ofD_(DTI). Note that the intermediate depth etch is performed to a depthequal to D_(DTI)−D_(STI). Photoresist mask 444 is then stripped, andprocessing continues in the manner described in connection with FIGS.3E-3P above.

FIGS. 5A and 5B are cross sectional views illustrating an alternatemethod for forming the desired shallow and deep trenches of the presentinvention.

As shown in FIG. 5A, a silicon nitride hard mask layer 520 is formedover substrate 300. Hard mask layer 520 generally has the same dimensionas hard mask layer 320, as presented above in connections with FIGS. 3Cand 3D. A photoresist mask 544 is formed over the resulting structure.Photoresist mask 544 covers those regions where shallow trenches are tobe formed, and exposes those regions where deep trenches are to beformed. An intermediate depth etch is performed through photoresist mask544 and hard mask layer 520, thereby forming intermediate depth trenches541 and 542. Note that the intermediate depth etch is performed to adepth equal to D_(DTI)−D_(STI).

As illustrated in FIG. 5B, photoresist mask 544 is then stripped, and ashallow trench isolation etch is performed through hard mask layer 520,thereby forming shallow trench region 543. Shallow trench region 543 hasa depth of D_(STI). The shallow trench isolation etch also extends theintermediate depth trenches 541 and 542 (hereinafter deep trench regions541 and 542), to a depth of D_(DTI). Processing then continues in themanner described above in connection with FIGS. 3E-3P.

Although the invention has been described in connection with severalembodiments, it is understood that this invention is not limited to theembodiments disclosed, but is capable of various modifications whichwould be apparent to a person skilled in the art. Thus, the invention islimited only by the following claims.

1. An embedded dynamic random access memory (DRAM) system comprising: asemiconductor substrate having a first conductivity type; a first set oftrench isolation regions having a first depth below an upper surface ofthe semiconductor substrate, the first set of trench isolation regionsbeing located in a first area of the semiconductor substrate; a secondset of trench isolation regions having a second depth, greater than thefirst depth, below an upper surface of the semiconductor substrate, thesecond set of trench isolation regions being located in a second area ofthe semiconductor substrate; a plurality of logic transistors fabricatedin the first area of the semiconductor substrate, wherein the logictransistors are isolated by the first set of trench isolation regions;and a plurality of dynamic random access memory (DRAM) cells fabricatedin the second area of the semiconductor substrate, wherein the DRAMcells are isolated by the second set of trench isolation regions.
 2. Theembedded DRAM system of claim 1, wherein the second depth is greaterthan the first depth by at least about 20 percent.
 3. The embedded DRAMsystem of claim 1, wherein each of the DRAM cells comprises a cellcapacitor having a capacitor electrode located at least partially in oneof the second set of trench isolation regions.
 4. The embedded DRAMsystem of claim 3, wherein the cell capacitor further includes adielectric layer located on a sidewall of one of the second set oftrenches.
 5. The embedded DRAM system of claim 3, wherein the cellcapacitor further includes an inversion layer located in the sidewall ofone of the second set of trenches.
 6. The embedded DRAM system of claim1, wherein the DRAM cells include access transistors having a first gatedielectric layer and cell capacitors having a capacitor dielectriclayer, and wherein the logic transistors have a second gate dielectriclayer, wherein the capacitor dielectric layer, the first gate dielectriclayer and the second gate dielectric layer are the same layer.
 7. Theembedded DRAM system of claim 1, wherein the DRAM cells include accesstransistors having a first gate dielectric layer and cell capacitorshaving a capacitor dielectric layer, and wherein the logic transistorshave a second gate dielectric layer, wherein the capacitor dielectriclayer and the first gate dielectric layer have a different thickness orcomposition than the second gate dielectric layer.
 8. The embedded DRAMsystem of claim 7, wherein the capacitor dielectric layer and the firstgate dielectric layer are the same layer.
 9. The embedded DRAM system ofclaim 7, wherein the capacitor dielectric layer and the first gatedielectric layer have different compositions and or thicknesses.
 10. Theembedded DRAM system of claim 1, wherein the DRAM cells include accesstransistors having a first gate dielectric layer and cell capacitorshaving a capacitor dielectric layer, wherein the capacitor dielectriclayer and the first gate dielectric layer have different thicknesses orcompositions.
 11. The embedded DRAM system of claim 3, wherein each ofthe DRAM cells further includes an access transistor having a gateelectrode, a first source/drain region coupled to the cell capacitor anda second source/drain region.
 12. The embedded DRAM system of claim 11,wherein the second source/drain region has a higher dopant concentrationthan the first source/drain region.
 13. The embedded DRAM system ofclaim 11, further comprising metal silicide located over the gateelectrode and the second source/drain region.
 14. The embedded DRAMsystem of claim 13, wherein the first source/drain region issubstantially free of metal silicide.
 15. The embedded DRAM system ofclaim 13, wherein the capacitor electrode is substantially free of metalsilicide.
 16. The embedded DRAM system of claim 11, wherein the gateelectrode and the capacitor electrode comprise polycrystalline silicon.17. The embedded DRAM system of claim 16, wherein the gate electrode andthe capacitor electrode are fabricated from the same layer ofpolycrystalline silicon.
 18. The embedded DRAM system of claim 11,wherein gate electrodes of the logic transistors, the gate electrodes ofthe access transistors and the capacitor electrodes are fabricated fromthe same layer of polycrystalline silicon.